During fin field-effect transistor (finFET) fabrication, a sea of fins can be patterned on a wafer, and then cut into individual devices. During this fin cut, however, channel strain becomes a concern, especially at scaled technology nodes where dimensions are reduced.
For instance, if the ends of the fins are cut after they are patterned, this can cause strain relaxation in cut fin segments. Strain relaxation impairs device performance by causing mobility degradation.
Also, during a subsequent replacement gate process, any sacrificial or dummy gates that are formed on a shallow trench isolation (STI) oxide between the cut ends of the fins are prone to collapse due to their high-aspect-ratio structure and undercutting of the underlying STI oxide. Dummy gate collapse can lead to spacer merging, incomplete spacer etch and/or complete dummy gate collapse, all of which are undesirable effects.
Accordingly, an improved replacement gate process which addresses the above-described challenges would be desirable.